The present invention relates to patterning lines in a silicon nitride layer formed on a semiconductor wafer or on another multilayer structure.
In semiconductor fabrication, it is often desirable to anisotropically etch thick dielectric films with high aspect ratio features (e.g., 4:1 or greater) without excessive erosion of an accompanying photoresist and with a high selectivity to oxide layers (e.g., silicon oxide). In many applications, the profile of the patterned nitride must be vertical. Current state-of-the-art nitride etch processes do not achieve etch profiles which are sufficiently vertical or etch processes which have sufficient selectivity to oxide.
As an example of such an application, formation of device gates by a damascene etch process requires that a nitride material be etched vertically to a thin thermal oxide material underneath the nitride. The stop layer of thermal oxide material is removed, and an even thinner gate oxide is grown in its place. The thickness of the stop layer is constrained by the ability to remove it without significant undercut, whereas the thickness of the grown gate oxide is determined by the device performance characteristics. A gate conductor is then deposited and polished down to the nitride.
In a standard gate etch process, a hard mask is needed to ensure adequate and controllable selectivity to the thin stop layer of thermal oxide material. Patterning of the hard mask with resist in place is the primary contributor to nested and isolated line variation. More particularly, FIGS. 1A and 1B show a standard (i.e., non-damascene) gate etch process of a multilayer structure 10. Structure 10 includes conductive gate stack 12, silicon nitride hard mask 14, nested lines 16a of a photoresist layer, and an isolated line 16b of the phototesist layer. After the photoresist layer is deposited on top of silicon nitride hard mask layer 14, the hard mask layer is etched to form a pattern in the hard mask layer corresponding to the pattern of the photoresist layer. The photoresist is subsequently stripped, leaving the patterned silicon nitride hard mask layer 14 shown in FIG. 1B. As can be seen from FIG. 1B, the portion of silicon nitride hard mask layer 14 which was under isolated lines 16b is eroded laterally during the mask etch process, and the silicon nitride hard mask layer displays significant across-chip line width variation (ACLV).
The difference in photoresist loading in the local region of the nested and isolated lines is the major contributing factor which causes the nested-to-isolated etch bias. For example, nearly 100% of the area near isolated line 16b is open (i.e., free of photoresist); in contrast, only about 50% of the area near nested lines 16a is open. The plasma chemistry is chosen to be reactive with silicon nitride, and the local concentration of reactive species (e.g., ions, radicals, and polymer precursors) in the etchant gas will be depleted in the vicinity of isolated line 16b due to the relatively high local loading of silicon nitride. The large area of nitride surrounding isolated line 16b acts as a sink for the reactive species.
Similarly, the local presence of more resist near nested lines 16a tends to shift the local plasma chemistry relative to the resist-poor regions near isolated line 16b. Specifically, the erosion of photoresist acts as a source of polymer precursors. Therefore, the region of hard mask layer 14 near isolated line 16b is exposed to a less polymerizing chemistry than that near nested lines 16a, thereby causing the lateral erosion in the etched hard mask under the isolated line as shown in FIG. 1B.
In a standard hard mask gate etch scheme as shown in FIGS. 1A and 1B, silicon is etched selective to thermal oxide (not shown, but formed as a thin layer over gate stack 12), typically in a chloride- or bromide-based etchant gas. Because the gate conductor etch is nonselective to the substrate (i.e., gate stack 12), any breakthrough of the thermal oxide leads to catastrophic attack of the underlying silicon. This risk becomes especially important as the gate oxide thickness is scaled down to increase device speed. As gate line widths are reduced, the aspect ratio of the gate stack increases. Stability of the gate stack in a hard mask gate etch scheme becomes an issue at very aggressive ground rules.
In the gate formation process, it is often necessary to strip a sacrificial thermal oxide layer and then grow a fresh gate oxide, as shown in FIG. 2. The thickness of a sacrificial thermal oxide layer 20 is constrained by the degree of anisotropy of the etch during stripping of the oxide. Any undercut of thermal oxide layer 20 will cause a foot 22 to form after the subsequent polysilicon 24 (gate conductor) fills the gate hole of a silicon nitride layer 26. Foot 22 degrades device performance.
Moreover, in any isotropic etch such as that shown in FIG. 4B, ions 51 are not accelerated toward a silicon nitride layer 50 in a uniform direction. Consequently, etching proceeds in every direction, undercutting a photoresist layer 52 and limiting the packing density of the devices. In FIG. 4B, silicon nitride layer 50 could be formed over a silicon substrate (not shown).
Although the art of etching silicon nitride is well developed, some problems inherent in this technology still exist. One particular problem is etching for high aspect ratio silicon nitride levels, while retaining high selectivity to both photoresist and oxide layers. Therefore, a need exists for a process for patterning silicon nitride with a high aspect ratio while maintaining high selectivity to photoresist and oxide layers and avoiding subsequent loss of image integrity.
To meet this and other needs, and in view of its purposes, the present invention provides a process for anisotropically etching a trench in a silicon nitride layer of a multilayer structure in a damascene etch scheme. The process comprises the steps of: exciting an etchant gas comprising a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent to form a high density plasma, in which the etchant gas has high nitride selectivity to a silicon oxide layer (formed over a substrate and below the nitride layer) and to a photoresist layer (formed over the nitride layer); and introducing the high density plasma to etch the exposed portion of the silicon nitride layer to form the trench extending to the silicon oxide layer.
In the present invention, the polymerizing agent is selected from the group consisting of at least one of CF4, C2F6, and C3F8; the hydrogen source is selected from the group consisting of at least one of CHF3, CH2F2, CH3F, and H2; the oxidant is selected from the group consisting of at least one of CO, CO2, and O2; and the noble gas diluent is selected from the group consisting of at least one of He, Ar, and Ne. In a preferred embodiment of the present invention, the oxidant comprises a carbon-containing oxidant component, such as CO2, and an oxidant-noble gas component, such as O2 in He. The concentrations of the constituents are selected to achieve an etchant gas having a high nitride selectivity to photoresist, such as at least about 3:1 and preferably at least about 4:1, and a high nitride selectivity to oxide, such as at least about 4:1 and preferably at least about 5:1.
According to another embodiment of the present invention, the power source used to control the directionality of the plasma, such as a radio frequency (RF) power source, is decoupled from the power source used to excite the etchant gas, such as a coil. Preferably, an RF power source is applied to the side of the structure opposite the side having the silicon nitride layer being etched.
The present invention is also directed to a process for making a metal oxide semiconductor field effect transistor (MOSFET) comprising the steps of: forming a silicon oxide layer over a substrate having at least two shallow trench isolation regions; forming a silicon nitride layer over the oxide layer; depositing a photoresist over the nitride layer so that the photoresist defines a window at which the nitride layer is exposed; exciting an etchant gas having constituents as described above to form a high density plasma; introducing the high density plasma to etch the exposed portions of the nitride layer to the oxide layer in a damascene etch process, thereby leaving a gate hole in the nitride layer at the window; depositing a gate conductor in the gate hole and removing at least a part of the silicon nitride layer wherein the gate conductor forms a gate pillar.
The present invention is also directed to an etchant gas composition used to etch a trench in a silicon nitride layer of a multilayer structure, in a damascene etch scheme. The etchant gas composition comprises a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent, as discussed above, and has high nitride selectivity to a silicon oxide layer and to a photoresist layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.